The present invention relates to semiconductor technology, and more specifically, to a semiconductor-based anti-fuse made from a stacked FinFET structure and a method of forming the same.
An anti-fuse is an electrical device that performs the opposite function of a fuse. Whereas a fuse initially has a low resistance and is designed to permanently break an electrically conductive path (typically when the current through the path exceeds a specified limit), an anti-fuse initially has a high resistance and is designed to permanently create an electrically conductive path (typically when the voltage across the anti-fuse exceeds a certain level).
Programmable on-chip anti-fuses are needed in many semiconductor integrated circuit applications. In some applications, it preferable to fabricate on-chip anti-fuses during stacked FinFET CMOS fabrication in order to minimize process cost and improve system integration. The breakdown voltage of conventional planar anti-fuses with a gate dielectric is too high. Also, planar anti-fuses use too much area compatible with current ground rules of 14 nm, 10 nm or 7 nm technology nodes. Therefore, there is a need for improved on-chip stacked FinFET compatible anti-fuses.